1. Field of the Invention
The present invention relates to an integrated circuit component and a method for fabricating the same, and more particularly, to a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
In the development of the integrated circuit components, high speed and low power electricity consumption are achieved by reducing the size of the component. However, the technique of reducing the component size is limited by the fabrication technique and high cost, thus a new technique of reducing the component size is desired to improve the device driving current. Accordingly, a method of using the stress control had been proposed to overcome the limitation of reducing the component size.
In a conventional method of using the stress control for improving the device performance, a high tensile or high compression silicon nitride layer used as a contact etching stop layer (CESL) is selectively formed on the substrate according to the N-channel or P-channel to improve the device driving current.
However, the method of improving the device performance by using the stress layer still leave some problems. In general, a compressive stress layer is formed on the P-channel device to improve the current gain and efficiency of the device. However, for some P-channel device, the device reliability is degraded. For example, if a compressive stress layer is formed on the input/output (I/O) P-channel MOS transistor (metallic oxide semiconductor field effect transistor), a threshold voltage (Vt) shift effect occurs, which would slow the negative bias temperature instability (NBTI), and further reduce the current gain and affect the device performance.